DMA SRC_INC not working as (I) expected - Raspberry Pi Forums

i'm playing around dma engine, it's not quite working expected.

i'm trying "repeat" 1 word 1 memory buffer - think memset() 32-bit value. figured setting dest_inc , clearing src_inc in dma control block.

i've set control block

code: select all

ti = (1 << 4)

(dest_inc = 1), seems source incrementing in "strange" way - repeating pattern of first 16 bytes of source in destination buffer (whereas expected first 4 bytes repeated)

i'm using dma channel 5 on mainline 4.4 kernel if matters, don't think does. code in kernel module, , i'm using "streaming" dma api sync buffers between cpu , dma.

here's annotated printouts code:

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/* allocate buffer, , dma_map */ noddy_open: dma_mapped vaddr da932000 -> paddr 0x1a932000 -> dma 0x1a932000  /* control block in ram */ ti:  00000010 /* dest_inc */ src: 1a932020 dst: 1a933000 len: 00000020 /* 32 byte transfer */ str: 00000000 nxt: 00000000  cb: /* dumped ram */ da932000: 10 00 00 00 20 20 93 1a 00 30 93 1a 20 00 00 00 da932010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  source buffer: /* initialised 1-31 */ da932020: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f da932030: 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f  dest buffer: /* zeroed */ da933000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 da933010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  /* transfer started , completed (too fast time) */ 32 byte transfer took 1000 ns  /* registers read peripheral */ dma registers: cs:  000f000a /* high prority, dreq , end */ cb:  00000000 ti:  00000010 /* dest_inc */ src: 1a932020 /* source address expected: not changed */ dst: 1a933020 /* dest address expected: (start + 32) */ len: 00000000 str: 00000000 nxt: 00000000  cb: /* before */ da932000: 10 00 00 00 20 20 93 1a 00 30 93 1a 20 00 00 00 da932010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  source buffer: /* before */ da932020: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f da932030: 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f  dest buffer: /* expected repeating "00 01 02 03" */ da933000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f da933010: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 

think above shows issue enough can post code if thinks - can explain behaviour? assuming wrong thing src_inc , dest_inc?

you'll notice addresses in '0x00000000-prefixed' bus-address region - returned dma apis. tried manually setting '0xc0000000-prefixed' bus addresses, made no difference. don't think should matter anyway dma engine isn't behind either of caches, i'm happy told i'm wrong.

i've tried fiddling forcing no write bursts , setting burst length = 1, seems make no difference.

dma reads in 128-bit stripes default. need set source width parameter 32-bit.

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