328P How to create IPBI(SGPIO) signal


hello~

i generate ipbi(sgpio) signal 328p 3.5" hdd backplene, can simulation riad card sgpio signal.
there 3 signal needs: sclock, sload, sdout.

sclock: 100khz , duty cycle=50% ,  provide , sync clock hdd backplene
sload:  start bit, inform hdd backplane, host deliver hdd satus.
sdout: hdd status
the data bit   xxx xxx xxx xxx (x=low or high) , total 12bit
                hdd__ (1)_(2)_(3)_(4)

may change 328p pwm clock frequcnce? ,  how sync sload , sdout when sclk @ high time or low time?

have 1 can teach me how do?

thanks every one.

update:

i modified timer , pwm pin can output 976hz (~1khz), how can output (sload) , (sdout) signal when sclk @ high edge?

code: [select]

    pinmode(3, output); 
    pinmode(11, output); 
    pinmode(2, output);
    tccr2a = _bv(com2a1) | _bv(com2b1) | _bv(wgm21) | _bv(wgm20); 
    tccr2b = _bv(cs22); 
    ocr2a = 128; 
    ocr2b = 128; 




thasnks every one.


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